Li Yu; Yang Tang; Yan Wang

Abstract In this paper, a novel 18-element asymmetric double-π equivalent circuit model for on-chip spiral inductors is proposed with corresponding direct parameter extraction. Meanwhile, the asymmetric characteristics of spiral inductors are analyzed by introducing a geometry-based optimization factor. To validate the proposed model and... [view more]

Abstract

In this paper, a novel 18-element asymmetric double-π equivalent circuit model for on-chip spiral inductors is proposed with corresponding direct parameter extraction. Meanwhile, the asymmetric characteristics of spiral inductors are analyzed by introducing a geometry-based optimization factor. To validate the proposed model and asymmetric analysis, two series of circular inductors with different number of turns and radii were fabricated and model parameters were extracted from S-parameters measurement up to 20GHz. The results show that this modeling methodology can achieve high accuracy extraction while offering simplification to previously reported methods.

Junming Li; Zheng Xu; Fujun Zhang; Suling Zhao; Dandan Song; Haina Zhu; Jinglu Song; Yongsheng Wang; Xurong Xu

Abstract Influences of electric fields on the emission from organic light-emitting diodes (OLEDs) based on poly(N-vinylcarbazole) (PVK) and 4′-bis(2-2diphenylvinyl)-1,1′-biphenyl (DPVBi) as the active emission layer are studied. Electroluminescence (EL) spectra of PVK:DPVBi (1... [view more]

Abstract

Influences of electric fields on the emission from organic light-emitting diodes (OLEDs) based on poly(N-vinylcarbazole) (PVK) and 4′-bis(2-2diphenylvinyl)-1,1′-biphenyl (DPVBi) as the active emission layer are studied. Electroluminescence (EL) spectra of PVK:DPVBi (1:1 w/w) films show one new emission peak locating at 640nm compared with its photoluminescence (PL) spectra. There may be exists an electroplex emission between the PVK and DPVBi under high electric field strength. The emission intensity of peaking at 640nm strongly depends on the driving voltage, and the ratio of electroplex emission intensity to exciton emission intensity (I _electroplex/I _exciton) increases with the increase of driving voltage.

Chen Gang; Qin YuFei; Bai Song; Wu Peng; Li ZheYang; Chen Zheng; P. Han

Abstract In this paper we report our research on DC and S parameter simulations and DC and RF characteristics experimental results of 4H–SiC MESFETs on a high purity semi-insulating substrate. 4H-SiC MESFETs were fabricated using home-grown epi structures. We designed our own devices process to... [view more]

Abstract

In this paper we report our research on DC and S parameter simulations and DC and RF characteristics experimental results of 4H–SiC MESFETs on a high purity semi-insulating substrate. 4H-SiC MESFETs were fabricated using home-grown epi structures. We designed our own devices process to fabricate n-channel 4H–SiC MESFETs with 200μm gate periphery. At a frequency of 2GHz and at 79V drain voltage, the maximum output power density CW is measured to be 7.8W/mm, with a gain of 11.9dB, and power-added efficiency 40%. The cut-off frequency (f_T ) and the maximum oscillation frequency (f _max) is 8.7GHz and 25.5GHz, respectively. The simulation result of f_T and f _max is 11.4GHz and 38.6GHz, respectively.

R. Mishra; D.E. Ioannou; S. Mitra; R. Gauthier; C. Seguin; R. Halbach

Abstract A study on the electrostatic discharge (ESD) behaviors of silicide blocked (Sblk) n and p channel MOSFETs is presented for a state-of-the-art 65nm SOI technology. It is observed that the charge in the floating body SOI MOSFETs helps to improve their ESD characteristics ... [view more]

Abstract

A study on the electrostatic discharge (ESD) behaviors of silicide blocked (Sblk) n and p channel MOSFETs is presented for a state-of-the-art 65nm SOI technology. It is observed that the charge in the floating body SOI MOSFETs helps to improve their ESD characteristics over the grounded body devices. The ESD behavior of the thin-oxide pMOSFETs shows failure current similar to the corresponding nMOSFETs but at the expense of higher power dissipation and higher parasitic bipolar transistor (pBJT) turn-on voltages. The study of gate-silicided (GS) and gate-non-silicided (GNS) nMOSFETs show that the GNS devices exhibit approximately 30% higher failure current than the similar sized GS devices. Transmission line pulsing (TLP) measurement with different stress pulse widths reveals that the self-heating effects are more pronounced in the GNS devices than the similar sized GS devices. The analytical thermal model for the bulk MOSFET when applied to the SOI MOSFET indicates that the high temperature region during the breakdown is not only at the drain-body junction but extends into the highly resistive drain silicide-blocked region.

Heung-Jae Cho; Sanghoon Lee; Byung-Gook Park; Hyungcheol Shin

Abstract Study of random telegraph noise in gate leakage current (Ig RTN) through thin gate oxide (2.6nm) as well as drain current random telegraph noise (Id RTN) has been conducted in MOSFET. RTN having two discrete current levels was observed in gate leakage current. Capture... [view more]

Abstract

Study of random telegraph noise in gate leakage current (I_g RTN) through thin gate oxide (2.6nm) as well as drain current random telegraph noise (I_d RTN) has been conducted in MOSFET. RTN having two discrete current levels was observed in gate leakage current. Capture and emission time constants of I_g fluctuation were found to depend on drain voltage as well as gate voltage. Capture time showed an increase while emission time showed a decrease with respect to gate voltage. New equations for extracting trap locations and its energy level were derived. The oxide trap extracted from I_g fluctuation was observed to react with the gate and have a deep trap energy level from the conduction band edge of oxide.

Wu-Te Weng; Yao-Jen Lee; Horng-Chih Lin; Tiao-Yuan Huang

Abstract This study examines the effects of plasma-induced damage (PID) both on advanced SiO2/poly-gate and Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal–oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates the PID... [view more]

Abstract

This study examines the effects of plasma-induced damage (PID) both on advanced SiO₂/poly-gate and Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal–oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates the PID impacts on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal–oxide-semiconductor field-effect transistors (MOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs with gate dielectric thickness scaling. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO₂/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for advanced high-k/metal-gate CMOS technology.

Nicholas M. Rada; Gregory E. Triplett

Abstract This study employed a thermal/spectral technique for examining self-heating effects in high-power light emitting diodes (LEDs). Here, high-power LEDs were thermally stressed, and the impact of self-heating effects was characterized in terms of luminal performance. Results from high-speed thermography demonstrated... [view more]

Abstract

This study employed a thermal/spectral technique for examining self-heating effects in high-power light emitting diodes (LEDs). Here, high-power LEDs were thermally stressed, and the impact of self-heating effects was characterized in terms of luminal performance. Results from high-speed thermography demonstrated that these thermal effects lead to degraded device performance, reduced power conversion efficiency, and power loss. The ability to monitor and quantify thermal transients using this approach is important for many optoelectronic and lighting applications. Temporal thermal and spectral characteristics were examined with the purpose of improving thermal management strategies.

Gajanan Dessai; Gennady Gildenblat

Abstract We present an alternative and computationally efficient description of the boundary between the trigonometric and hyperbolic solutions of the Poisson–Boltzmann equation for the independent-gate asymmetric DGFET. In particular, we demonstrate that this boundary consists of two curves and provide the explicit expression for both of them... [view more]

Abstract

We present an alternative and computationally efficient description of the boundary between the trigonometric and hyperbolic solutions of the Poisson–Boltzmann equation for the independent-gate asymmetric DGFET. In particular, we demonstrate that this boundary consists of two curves and provide the explicit expression for both of them in terms of the Lambert W function.

Marina Antoniou; Florin Udrea; Friedhelm Bauer

Abstract In this paper we present a new design approach which dramatically improves the robustness of power semiconductor device against cosmic rays induced breakdown. This failure mode occurs during continuous operation at a DC rail voltage, which in practice is well below the breakdown rating (typically half of ... [view more]

Abstract

In this paper we present a new design approach which dramatically improves the robustness of power semiconductor device against cosmic rays induced breakdown. This failure mode occurs during continuous operation at a DC rail voltage, which in practice is well below the breakdown rating (typically half of the breakdown). This failure is more prominent for higher breakdown rated devices (above 2kV) and represents one of the main causes of concern, especially if the power systems are operated at higher altitude. Using a mathematical model for the calculation of the cosmic ray breakdown failure rate proposed by Zeller [1] , we show that by employing a SuperJunction structure in the drift region of a high voltage diode we can achieve a great improvement in the robustness of the device against cosmic ray radiation. Since the cosmic ray failure rate is strongly dependent on the electric field distribution, the two-dimensional nature of the SuperJunction electric field with lower peaks and more even distribution offers a huge advantage over the use of standard PiN devices. Finally, a physical two-dimensional electric field model for the SuperJunction structures is developed which is then imported into Zeller’s model to compute the cosmic ray failure rate for different DC voltage rails.

Sungho Kim; Oktay Yarimaga; Sung-Jin Choi; Yang-Kyu Choi

Abstract Resistance random access memory (RRAM) consisting of stacked Al/TiO x /Al structure is demonstrated on a flexible and transparent substrate. To improve cell to cell uniformity, TiO x formed by atomic layer deposition is used for resistive switching material. The simple cross-bar structure of... [view more]

Abstract

Resistance random access memory (RRAM) consisting of stacked Al/TiO _x /Al structure is demonstrated on a flexible and transparent substrate. To improve cell to cell uniformity, TiO _x formed by atomic layer deposition is used for resistive switching material. The simple cross-bar structure of the RRAM and good ductility of aluminum electrode results in excellent flexibility and mechanical endurance. Particularly, bipolar and unipolar resistive switching (BRS, URS) behavior appeared simultaneously were investigated. Depending on the current compliance, BRS or URS could be selectively observed. Furthermore, the permanent transition from BRS to URS was observed with a specific current compliance. To understand this transition behavior, the γ-ray irradiation effect into resistive switching is primarily investigated.

A. Datta; S. Mahapatra

Abstract Scaling prospects of pre-cycled 2-bit channel engineered SONOS flash EEPROM cells are studied on cells co-doped with compensation and halo implant. The compensation implant is shown to work in long channel cells to optimize bit coupling, read disturb, and program speed. However, co-... [view more]

Abstract

Scaling prospects of pre-cycled 2-bit channel engineered SONOS flash EEPROM cells are studied on cells co-doped with compensation and halo implant. The compensation implant is shown to work in long channel cells to optimize bit coupling, read disturb, and program speed. However, co-doping with compensation implant fails at short channel length to reduce read disturb thus bit coupling at safe read V _D. The junction engineering scheme is shown as the possible alternative for successful scaling of cells to simultaneously reduce read disturb and bit coupling but at the expense of program speed, which seems detrimental for deep scaling of cells.

Kyu-Heon Cho; Young-Shil Kim; Jiyong Lim; Young-Hwan Choi; Min-Koo Han

Abstract We proposed the AlGaN/GaN high electron mobility transistors (HEMTs) employing the mesa field plate and carried out the detailed numerical simulation of device operation using ISE-TCAD. The reduction of peak electric field is required to achieve the high breakdown voltage of AlGaN/GaN HEMTs. Proposed... [view more]

Abstract

We proposed the AlGaN/GaN high electron mobility transistors (HEMTs) employing the mesa field plate and carried out the detailed numerical simulation of device operation using ISE-TCAD. The reduction of peak electric field is required to achieve the high breakdown voltage of AlGaN/GaN HEMTs. Proposed AlGaN/GaN HEMT with both gate and mesa field plates simultaneously reduced the electric field concentration at the gate and the drain edge by decreasing the potential gradient along the 2-DEG channel. As the peak electric field at the drain edge was decreased, the breakdown voltage was increased by 66% compared with the AlGaN/GaN HEMT with the gate field plate only. The breakdown voltage could be increased without sacrificing any other forward characteristics due to the SiO₂ passivation layer.

Abbas Jamshidi-Roudbari; Po-Chin Kuo; Miltiadis K. Hatalis

Abstract In an effort to increase the integration level of large area digital and mixed-signal systems on flexible substrate, we designed and successfully fabricated and characterized a 3-bit flash analog to digital converter on stainless steel foil substrate. High quality laser crystallized polysilicon Thin Film Transistors (... [view more]

Abstract

In an effort to increase the integration level of large area digital and mixed-signal systems on flexible substrate, we designed and successfully fabricated and characterized a 3-bit flash analog to digital converter on stainless steel foil substrate. High quality laser crystallized polysilicon Thin Film Transistors (TFT) as well as carefully designed comparator circuit made it possible for a high performance flash ADC with maximum sampling rate of 3Ms/s to be developed on stainless steel foil substrate. Both Integral and Differential Non-Linearity were extracted to be less than or equal to 0.25th of a Least Significant Bit (LSB), which makes it possible to increase the number of bits to 5-bits while keeping the same design structure and operating voltages. The same 3-bit design can also be used along with a 3-bit digital to analog converter in a two-step flash ADC structure to implement a 6-bit converter.

A. Kosarev; S. Rumyantsev; M. Moreno; A. Torres; S. Boubanga; W. Knap

Abstract SiGe-based bolometers originally designed for infrared operation have been tested as detectors of terahertz radiation. The obtained values of the responsivity and noise equivalent power show that these detectors can compete with conventional room temperature detectors such as pyroelectric detectors and Golay cells having an advantage in ... [view more]

Abstract

SiGe-based bolometers originally designed for infrared operation have been tested as detectors of terahertz radiation. The obtained values of the responsivity and noise equivalent power show that these detectors can compete with conventional room temperature detectors such as pyroelectric detectors and Golay cells having an advantage in their compatibility with the CMOS technology.

Philippe Gaubert; Akinobu Teramoto; Tadahiro Ohmi

Abstract The paper deals with the investigation of the hole mobility in p-channel MOS transistors fabricated on (110) oriented silicon wafers. At first, we showed that the conventional methods used to extract the conduction parameters such as the low field mobility or the mobility attenuation factor could... [view more]

Abstract

The paper deals with the investigation of the hole mobility in p-channel MOS transistors fabricated on (110) oriented silicon wafers. At first, we showed that the conventional methods used to extract the conduction parameters such as the low field mobility or the mobility attenuation factor could not be applied for this orientation. This is the consequence of a change in the origin of the scattering mechanisms limiting the effective mobility. While in the case of the (100) p-MOS transistors the phonon scattering is the unique mechanism defining the effective mobility, this one is characterized by an arrangement of the Coulomb scattering, phonon scattering as well as surface roughness scattering in the case of the (110) p-MOS transistors. A consequence is that the modelling of the mobility must include all three mechanisms in order to simulate accurately the static characteristics of Si(110) p-MOS transistors, making then a necessity for us to develop a more adapted model. Finally, it has been seen that the effective mobility in the p-MOS transistors on Si(110) is not only higher than the one in the p-MOS transistors on Si(100) but appears to be almost electric independent over the usual range of polarisations making it more stable and then pleading even more in this new orientation’s favour.

Richard K. Oxland; Gary W. Paterson; Andrew R. Long; Faiz Rahman

Abstract The behaviour of an InP/InGaAs heterojunction bipolar transistor stack in a magnetic field is described here with reference to various surface modifications. These include surface passivation with sulphur-based species, surface amorphisation with plasma-induced ion bombardment and inclusion of three-dimensional ferromagnetic thin-film structures on... [view more]

Abstract

The behaviour of an InP/InGaAs heterojunction bipolar transistor stack in a magnetic field is described here with reference to various surface modifications. These include surface passivation with sulphur-based species, surface amorphisation with plasma-induced ion bombardment and inclusion of three-dimensional ferromagnetic thin-film structures on the surface of the device. The structure, fabrication and modelling of the device is described in brief, followed by the results of transport and transduction experiments on the hybrid ferromagnet-bipolar transistor device. The results clearly show the important role played by surface conditions on surface and near-surface electron interactions brought about by Lorentz deflection of transport current in bipolar transistors and the potential for using these effects to measure the strength of magnetic fields. A new type of compound semiconductor integrated ferromagnet-bipolar transistor magnetic field sensor, based on these processes, is presented.

Monuko du Plessis; Pieter Rademeyer

Abstract In this paper a novel technique to analyze the low-voltage breakdown regime of silicon diodes is presented. It is shown that the field emission tunnel current component of the reverse current does not cause energy transitions of carriers, and therefore will not emit photons. All photons ... [view more]

Abstract

In this paper a novel technique to analyze the low-voltage breakdown regime of silicon diodes is presented. It is shown that the field emission tunnel current component of the reverse current does not cause energy transitions of carriers, and therefore will not emit photons. All photons being emitted from the pn junction are due to avalanche electroluminescence as a result of hot carrier energy relaxation processes. Measuring the light intensity output as a function of reverse current, the two current components (field emission and impact ionization) can be extracted as a function of reverse voltage. The experimental results were verified using the differential dynamic impedance method, as well as fitting a theoretical model to the extracted tunnel current. The temperature coefficient of current also indicated the transition from tunneling to avalanche.

Gun Woo Hyung; Jaehoon Park; Jun Ho Kim; Ja Ryong Koo; Young Kwan Kim

Abstract We propose a viable method of improving the storage stability of pentacene organic thin-film transistors (OTFTs) by the formation of polyimide (PI) passivation layer on the top of OTFTs. Solution-processed passivation layers can degrade the performance of OTFTs owing to fatal damage caused by ... [view more]

Abstract

We propose a viable method of improving the storage stability of pentacene organic thin-film transistors (OTFTs) by the formation of polyimide (PI) passivation layer on the top of OTFTs. Solution-processed passivation layers can degrade the performance of OTFTs owing to fatal damage caused by chemical solvents on organic semiconductors. In this study, the vapor deposition polymerization method, which is in situ dry process, is introduced to fabricate a patterned PI passivation layer. It is shown that the presented PI passivation layer is effective for protecting moisture in ambient air and the characteristic variation of OTFT is almost negligible even after the passivation process. Under an average relative humidity of 50% at room temperature, the OTFT with such a PI passivation layer exhibits an extended half-life time of about 360h in its switching behavior, while less than 24h for the device without any passivation layer.

Yifeng Gu; Zhitang Song; Ting Zhang; Bo Liu; Songlin Feng

Abstract Se-doped GeSb were investigated for the possible applications in three-level phase-change memory. Ge15Sb85Se0.8, as a typical composition, has two abrupt drops of electrical resistance during an in situ temperature-dependent resistance measurement. The large-resistance change in the two drops and the stable... [view more]

Abstract

Se-doped GeSb were investigated for the possible applications in three-level phase-change memory. Ge₁₅Sb₈₅Se_0.8, as a typical composition, has two abrupt drops of electrical resistance during an in situ temperature-dependent resistance measurement. The large-resistance change in the two drops and the stable middle-resistance state make Ge₁₅Sb₈₅Se_0.8 a good candidate for the three-level data storage applications. Three-level phase-change memory based on Ge₁₅Sb₈₅Se_0.8 has been fabricated and demonstrated. X-ray diffraction patterns indicate that the reason for the middle-resistance state in Ge₁₅Sb₈₅Se_0.8 is due to the incomplete crystallization.

Golap Kalita; Matsushima Masahiro; Wakita Koichi; Masayoshi Umeno

Abstract Organic bulk heterojunction solar cells based on poly(3-hexylthiophene) (P3HT) and the fullerene derivative (PCBM) were fabricated and nanostructured morphology were investigated. Bulk heterojunction solar cells were fabricated with concentration ratio 1:0.5, 1:1 and 1:2 of P3HT and PCBM. Nanostructured... [view more]

Abstract

Organic bulk heterojunction solar cells based on poly(3-hexylthiophene) (P3HT) and the fullerene derivative (PCBM) were fabricated and nanostructured morphology were investigated. Bulk heterojunction solar cells were fabricated with concentration ratio 1:0.5, 1:1 and 1:2 of P3HT and PCBM. Nanostructured morphology of P3HT:PCBM composite films were investigated with annealing temperature and variation of composition ratio, which were correlated with device performance. Fabricated solar cells annealed at 150°C show much better device performance than that of the cells without annealing. Transmission electron microscopy (TEM) study shows formation of PCBM nanocrystals in the P3HT composite film with annealing. The formations of elongated PCBM nanocrystals provide an efficient percolation path for the electron, thereby improving device performance. Better device performance was observed with 1:1 as compared to 1:0.5 and 1:2 concentration ratios of P3HT and PCBM. With decrease in PCBM content, there were no efficient percolation paths for electron; on the other hand there were poorer intermolecular packing with increased PCBM content leading to lower device performance.

Yue Zhao; Zhiyong Lv; Zhao Li; Xiaoyan Liang; Jiahua Min; Linjun Wang; Weimin Shi; Yongyue Liu

Abstract In this paper, the photoluminescence of as-prepared porous silicon were investigated. The visible light emission is associated with surface defects states of porous silicon. The hydrogen atoms on porous silicon surface can passivate irradiative centers and lead to the increase of emission intensity, which can be... [view more]

Abstract

In this paper, the photoluminescence of as-prepared porous silicon were investigated. The visible light emission is associated with surface defects states of porous silicon. The hydrogen atoms on porous silicon surface can passivate irradiative centers and lead to the increase of emission intensity, which can be proved by the microwave-detected photoconductivity decay measurements.

Weijun Luo; Xiaojuan Chen; Hui Zhang; Guoguo Liu; Yingkui Zheng; Xinyu Liu

Abstract A C-band linear power amplifier is successfully developed with a one-chip 2mm AlGaN/GaN high electron mobility transistors (HEMTs). Two kinds of matching circuits for the linear power amplifier are compared. Besides, stabilization methods for the amplifier are also discussed. At 5.4GHz, ... [view more]

Abstract

A C-band linear power amplifier is successfully developed with a one-chip 2mm AlGaN/GaN high electron mobility transistors (HEMTs). Two kinds of matching circuits for the linear power amplifier are compared. Besides, stabilization methods for the amplifier are also discussed. At 5.4GHz, the developed GaN HEMTs linear power amplifier delivers a 37.2dBm (5.2W) cw P1dB output power with 9dB linear gain and 55.7% maximum power-added efficiency (PAE) with a drain voltage of 25V. To our best knowledge, the achieved PAE is the state-of-the-art result ever reported for 2mm gate width single die GaN-based hybrid microwave integrated power amplifier at C-band.

Peizhen Yang; W.S. Lau; Seow Wei Lai; V.L. Lo; S.Y. Siah; L. Chan

Abstract We investigate the effects of switching from 〈110〉 to 〈100〉 channel orientation on NMOS and PMOS transistors. For NMOS transistors, we have experimentally demonstrated that there is negligible electron mobility degradation after the switching. The decrease in on-current (I on) of 〈100〉 ... [view more]

Abstract

We investigate the effects of switching from 〈110〉 to 〈100〉 channel orientation on NMOS and PMOS transistors. For NMOS transistors, we have experimentally demonstrated that there is negligible electron mobility degradation after the switching. The decrease in on-current (I _on) of 〈100〉 NMOS transistors is caused by an increase in the effective channel length due to a reduction in the lateral ion channeling of the source/drain extension implants and the halo implants. For PMOS transistors, the increase in hole mobility dominates over the reduction of lateral ion channeling, and thus I _on of 〈100〉 PMOS transistor increases. By exploiting the stress insensitivity of 〈100〉 PMOS transistors, we can use a single tensile liner to improve NMOS transistors while not degrading PMOS transistors instead of using a more complicated process involving a tensile stress liner for NMOS transistors and a compressive liner for PMOS transistors.

H.-K. Lin; Y.-C. Lin; F.-H. Huang; T.-W. Fan; P.-C. Chiu; J.-I. Chyi; C.-H. Ko; T.-M. Kuan; M.-K. Hsieh; W.-C. Lee; C.H. Wann

Abstract Conventional InAs/AlSb HEMTs suffer from chemical instability in materials and high kink current. To avoid these drawbacks, this work proposes a novel layer structure of an InAsSb/AlSb HEMT and a novel two-step passivation process. Performance improvements are reduced dc output conductance by approximately 4.... [view more]

Abstract

Conventional InAs/AlSb HEMTs suffer from chemical instability in materials and high kink current. To avoid these drawbacks, this work proposes a novel layer structure of an InAsSb/AlSb HEMT and a novel two-step passivation process. Performance improvements are reduced dc output conductance by approximately 4.6 times at V _DS=0.5V and I _D=100mA/mm, and gate leakage to 1×10⁻³mA/mm from 4 at V _GS=−1.2V and V _DS=0.8V compared with those of two InAs/AlSb HEMTs, one with the conventional one-step and the other with the proposed two-step passivation process. Both dc and rf performances show strong evidences of impact ionization suppression.

Hai Zhong Zhang; Hong Tao Cao; Ai Hua Chen; Ling Yan Liang; Zhi Min Liu; Qing Wan

Abstract We report on the fabrication of bottom-gate thin-film transistors (TFTs) using indium-oxide (In2O3) thin films as active channel layers. The films were deposited on thermally grown silicon dioxide (SiO2)/n-type silicon (Si) at room temperature (RT) by radio-frequency ... [view more]

Abstract

We report on the fabrication of bottom-gate thin-film transistors (TFTs) using indium-oxide (In₂O₃) thin films as active channel layers. The films were deposited on thermally grown silicon dioxide (SiO₂)/n-type silicon (Si) at room temperature (RT) by radio-frequency (RF) magnetron sputtering. The effect of deposition pressure on the performance of In₂O₃-TFTs was investigated in detail. A significant improvement of the device performance was observed for In₂O₃-TFTs with the decrease of the working pressure, which is attributed to enhanced densification, better surface morphology of the In₂O₃ channel layers prepared at lower deposition pressure. The fabricated TFT with optimal device performance exhibited a field-effect mobility (μ _FE) of 31.6cm²V⁻¹s⁻¹, a drain current on/off ratio of ∼10⁷, a low off drain current of about 10⁻¹⁰A and a threshold voltage of 7.8V. Good device performance and low processing temperature make the In₂O₃-TFTs suitable for the potential applications in the transparent electronics.

Kyung-Min Yoon; Ki-Yeon Yang; Kyeong-Jae Byeon; Heon Lee

Abstract TiO2 nano-patterns were formed on the indium-tin-oxide (ITO) layer of GaN based light emitting diodes (LEDs) without a residual layer using a sol-imprinting process. A polydimethylsiloxane mold replicated from a Si master was used as the imprint stamp for the sol-imprinting ... [view more]

Abstract

TiO₂ nano-patterns were formed on the indium-tin-oxide (ITO) layer of GaN based light emitting diodes (LEDs) without a residual layer using a sol-imprinting process. A polydimethylsiloxane mold replicated from a Si master was used as the imprint stamp for the sol-imprinting process. The light extraction efficiency of LEDs was enhanced by the TiO₂ nano-patterns formed on the ITO layer because the TiO₂ nano-patterns locally modulated the refractive index of the ITO layer and enhanced the scattering of light at the ITO layer. Consequently, directly fabricated TiO₂ nano-patterns on the ITO layer can esoln hance the light extraction efficiency of LEDs without plasma-induced damage.

Han Cheng Lee; Yan Kuin Su; Jia Ching Lin; Yi Cheng Cheng; Ta Ching Li; Kuo Jen Chang

Abstract Aluminum indium gallium nitride (AlInGaN) metal–insulator–semiconductor (MIS) ultraviolet-C (UV-C) photodetectors (PDs) with a Ni/Ir/Au multilayer contact were proposed and fabricated. The inserting layer of the high work function metal (Ir) can significantly reduce the dark current of ... [view more]

Abstract

Aluminum indium gallium nitride (AlInGaN) metal–insulator–semiconductor (MIS) ultraviolet-C (UV-C) photodetectors (PDs) with a Ni/Ir/Au multilayer contact were proposed and fabricated. The inserting layer of the high work function metal (Ir) can significantly reduce the dark current of PDs and enhance the device performance, which can be attributed to the formation of IrO₂ in multilayer contact. With a 3.5V reverse bias, it was found that the dark current densities of PDs with a Ni/Au conventional contact and a Ni/Ir/Au multilayer contact were 3.7×10⁻⁸A/cm² and 8.3×10⁻⁹A/cm², respectively. Although the responsivities of these two different PDs are almost the same, the rejection ratio of AlInGaN MIS PD with a Ni/Ir/Au contact was larger than that of PD with a Ni/Au contact.

M. Montes; A. Guzmán; A. Trampert; A. Hierro

Abstract The electrical and optical characteristics of a set of MBE-grown 1.3μm emitting GaInNAs/GaAs quantum well (QW) resonant cavity light-emitting diodes (RCLEDs) have been analyzed as a function of the growth temperature of the distributed Bragg reflector (DBR) and the contact alloying... [view more]

Abstract

The electrical and optical characteristics of a set of MBE-grown 1.3μm emitting GaInNAs/GaAs quantum well (QW) resonant cavity light-emitting diodes (RCLEDs) have been analyzed as a function of the growth temperature of the distributed Bragg reflector (DBR) and the contact alloying. The RCLEDs consist of a λ-long microcavity delimited on one side by an 8-pair AlAs/GaAs DBR and on the opposite side by a metallic mirror, with the QW located at one of the antinodes of the standing wave. The structures are designed for extraction of the light through the substrate. Room-temperature electroluminescence at 1.3μm is demonstrated with 38% In and 1.3% N in the quantum well. It is found that the RCLEDs with the DBR grown at the lowest temperature of 670°C show a lower differential slope efficiency and degraded current–voltage characteristics, i.e. higher ideality factor, lower shunt resistance and lower threshold voltage. This degradation can be explained to arise from the higher roughness observed in the DBRs grown at 670°C, which likely enhance the formation of point defects and compositional inhomogeneities in the quantum well. Alloying of the ohmic contacts also results in a widening of the electroluminescence emission, probably due to the degradation of the top metallic mirror sharpness caused by the diffusion of the metal into the GaAs. The best results in terms of differential slope efficiency and electrical characteristics are obtained when the DBRs are grown at 750°C and the contacts are left non-alloyed.

Seungyeon Lee; Hyunjoo Lee; Sojeong Kim; Seungjun Lee; Hyungsoon Shin

Abstract Spin-transfer-torque (STT) switching in magnetic-tunnel-junction (MTJ) has important merits over the conventional field induced magnetic switching (FIMS) MRAM in avoiding half-select problem, and improving scalability and selectivity. Design of MRAM circuitry using STT-based MTJ elements requires an accurate circuit... [view more]

Abstract

Spin-transfer-torque (STT) switching in magnetic-tunnel-junction (MTJ) has important merits over the conventional field induced magnetic switching (FIMS) MRAM in avoiding half-select problem, and improving scalability and selectivity. Design of MRAM circuitry using STT-based MTJ elements requires an accurate circuit model which exactly emulates the characteristics of an MTJ in a circuit simulator such as HSPICE. This work presents a novel macro-model that fully emulates the important characteristics of STT-based MTJ. The macro-model is realized as a three terminal sub-circuit that reproduces asymmetric resistance versus current (R–I) characteristics and temperature dependence of R–I hysteresis of STT-based MTJ element.